Binary parallel adder utilizing sequential and simultaneous carry generation



Oct. 1, 1963 H. J. HElJN 3, 0 ,8 7

BINARY PARALLEL ADDER UTILIZING SEQUENTIAL AND SIMULTANEOUS CARRY GENERATION Filed Feb. 10, 1959 4 Sheets-Sheet 1 FIGJ I 4 4 4 4 3 i o 1 2 Z: z 0 X x 1 X0 3 8 6 @n 6 .E-. 6 E]- 60 Y Y Y y INVENTOR HERMAN JACOB HEIJN AGENT Oct. 1, 1963 H. J. HElJN 3,105,897

BINARY PARALLEL ADDER UTILIZING SEQUENTIAL AND SIMULTANEOUS CARRY GENERATION Filed Feb. 10, 1959 4 Sheets-Sheet 2 INVENTOR.

Fl G.4b

By HERMAN J. HEIJN w ma i;

AGE.

06h 1963 H. J. HEIJN ,105,897

BINARY PARALLEL ADDER UTILIZING SEQUENTIAL AND SIMULTANEOUS CARRY GENERATION Filed Feb. 10, 1959 4 Sheets-Sheet 3 5 E INVENTOR. 1o 11 13 J. HEIJN BY MR AGENT Oct. 1,5963 H J HEIJN 3,105,897

BINARY PARALLEL ADIiER' UTILIZING SEQUENTIAL AND SIMULTANEOUS CARRY GENERATION Filed Feb. 10, 1959 4 Sheets-Sheet 4 w y-I mg? 10 |T 1o 10 'FIG.8 I

HERMAN JACOB HEIJN it ,EKW

AG NT This invention relates to an improvement in or a modification of the invention described and claim in United States patent application No. 708,917, filed January 14,

1958, now Patent No. 3,056,551, wherein there is disclosed an arithmetic unit for a digital computer built up of gates, which receives information about the digits of a plurality of numbers called operands and converts this information into information about the digits of the result of an arithmetical operation performed on the operands. The arithmetic unit is subdivided into a plurality of sections, each of which corresponds to a single digit place or a plurality of consecutive digit places of the operands and of the result, the carry being formed sequentially within these sections; each section, with the possible exception of the first, is provided with an input carry producer which produces the carry of the section concerned, which input carry producer receives information about the individual digits of the operands at all digit places of the immediately preceding section and, with the possible exception of the first, also receives information about the input carry of the section preceding e immediately preceding section; the latter input carry is produced in turn by the immediately preceding input carry producer, so that the production of the input carries is elfected simultaneously so far as the digits at the digit places of the immediately preceding section are concerned but sequentially so far as the digits at the digit places are concerned with correspond to the sections preceding this immediately preceding section. The arrangement is such that the information about the digits of the result which correspond to the ends of the sections are all produced through about the same maximum number of gates in series so that the entire information about these digits of the result is produced substantially simultaneously. When performing some conditional operations, for example subtractions in division, it is of importance that the sign of the result of the operation being performed be available very rapidly since the nature of the next operation may depend on this sign. The sign of the result is determined by the last digit (the digit at the extreme left) of the result and consequently also by the carry produced from all the preceding di its. Hence, it is of importance for this carry (hereinafter to be referred to as end carry) to be available as rapidly as possible. However, in the arithmetic unit described in Patent No. 3,056,551 the end carry may be produced through all the input carry producers, and this takes an appreciable amount of time. it is an object of the present invention to obviate this disadvantage. An arithmetic unit in accordance with the invention includes an end carry producer which receives information about the digits at all digit places preceding the last place and from this information produces the end carry simultaneously. In the following description, the terms digit place and order are interchangeable.

In order that the invention may readily be carried out, embodiments of an arithmetic unit for a digital computer will now be explained more fully, by way of example, with reference to the accompanying drawings, in which:

FIG. 1 shows the general principle of an arithmetic unit of a digital computer;

ice

FIG. 2 shows a more detailed diagram of the arithmetic unit of known digital computers;

FIG. 3 shows a diagram of some details of the arithmetic unit shown in FIG; 2;

FIG. 4, composed of FIGS. 4a and 4b, shows a diagram of thethird and dourth sections of a summation device such as shown in United States patent application No. 708,917;

FIG. 5 shows the diagram of one embodiment of the input carry producer of the third section of a summation device in accordance with, the said patent application No. 708,917;

FIG. 6 shows the diagram of one embodiment of a summation device according to the instant application;

FIG. 7 shows the diagram of one embodiment of the input carry producer of the third section of the summation device shown in FIG. 6; and

FIG. 8 shows the circuit diagram of one embodiment of the end carry producer of the summation device shown in FIG. 6.

In FIG. 1, reference numerals l and 2 denote two registers in which numbers it and y can be stored, and reference numeral 3 denotes an arithmetic unit. The latter receives information from the registers 1 and 2 and produces the result 1 of the arithmetical operation performed on the numbers or operands x and y. This is shown in the figure by lines including arrows drawn from the registers to the arithmetic unit. From the instant at which the information about the result 2 is completely present in the arithmetic unit, the result can be transferred to a member, for example the register 1, of the computer. This transfer of the number present in the arithmetic unit is efiected by the action of a control pulse, which is supplied with a constant repetition period T by a pulse generator associated with the computer. This repetition period T must exceed the greatest time interval required by the arithmetic unit for producing the result. The lower limit thus set to the repetition period frequently lies, for computers having many digit places, considerably above the lower limit of the period by which the digits in the registers 1 and 2 can be varies, so that the computing rate of the computer can be increased by increasing the computing rate of the arithmetic unit.

FIG. 2 shows in greater detail an arithmetic unit for performing additions in the binary scale of notation. The registers l and 2 comprise bistable members 4 4 4 5 5 5 which correspond to the digit places of the operands x and y. Each stable condition of the members 4;, 5 corresponds to a digit (0 and 1 in the binary scale of notation) at a given digit place. The arithmetic unit 3, in the present case the sum producer, comprises a plurality of adders 6 6 6 with interposed carry producers 8 8 8 Finally the register 1 comprises a plurality of control members 7 7 '7 Each adder 6 receives information from the bistable members 4 and 5 at the same digit place and from the preceding carry producer 8 (with the exception of the first adder 6 if this is not preceded by a carry producer, as is the case in calculations using a so-called end-around-carry). Each adder 6 supplies information to the control member 7 at the same digit place and to the subsequent carry producer 81,14 (with the exception of the last adder 6 if this is not followed by a carry producer, as is the case in calculations using a socalled end-around-carry). Thus, a group of members 4 S 6 7 corresponds to each digit place: 4 5 6 7 correspond to the units or 'Z -OIdBI digits, i.e., to the digit position 0; 4 5 .6 7 correspond to the 2 -order digits, i.e., to the digit position 1; 4 5 6 7 correspond to the 2 -order digits, i.e., to the digit position'2; etc.

Each carry producer 8i 1;1 receives information (in FIG. 2 through the preceding adder 6 from the preceding bistable members 4 5 and from the preceding carry producer 81414 (except the first carry producer 80,1, which is not preceded by a carry producer). Each carry producer supplies information to the succeeding adder 6 and (in FIG. 2 through this adder 6 to the succeeding carry producer (with the exception of the last carry producer 8 which is not succeeded by a carry producer). As will be described more fully hereinafter, the adders and carry producers may also receive indirect information about the digits x and y of the numbers at and y.

The digital arithmetic unit shown in FIG. 2 operates as follows. The two numbers to be added to each other x x x and y y y (in binary notation the numbers xzx +2x +2 x and where x and y can only assume the values and l) are stored in the registers 1 and 2 in a manner which is immaterial to the operation of the arithmetic unit, i.e. the member 4; is brought into the condition corresponding to the digit x; and the member 5 into the condition corresponding to the digit y Information about the con ditions of the members 4 4 4 5 5 5 is fed to the adders 6 6 6 for example in the form of voltages. Now in the adder 6 information is produced about the first digit Z0 of the sum 2 and in the carry producer 8 information is produced about the carry 0 resulting from this addition. Subsequently in the adder 6 information is produced about the second digit Z1 of the sum z and in the carry producer 8 information is produced about the carry 0 resulting from this addition. Then in the adder 6 information is produced about the third digit Z2 of the sum 2 and in the carry producer 8 information is produced about the carry c resulting from this addition. This process continues in an analogous manner until information about all digits Z Z1, Z2 of the sum 2276+) is available. Subsequently a control pulse is applied, through a conductor 9, to all control members '7 7 7 with the result that the information available about the digits Z0, Z1, Z2 is transferred to the members 4 4 4 which consequently assume the conditions corresponding to these digits. If desired, the computer may comprise control members causing the sum 2 to be transferred to a member other than the register 1, for example to a main storage or auxiliary storage. From the foregoing it is apparent that the addition performed by this summation device is effectively a sequential operation, that is to say, takes place digit after digit. This is true even though the digits of the two numbers to be added are simultaneously supplied to the arithmetic unit for, in the most unfavorable case, the carry ripples over all the digit positions. Storing a number in a register can, but need not, be effected as a simultaneous operation, that is to say, all the digits can be stored in the register simultaneously. Assuming now that:

T :minimum time interval, in which. the members 4 5,

can be made to pass completely from one stable condition to another stable condition;

T zminimum time interval in which the members 4 5 after the occurrence of a control pulse, can supply information about the new stable condition;

T zminimum time interval in which each of the logical members 6 8 can supply output information after the reception of input information. If the arithmetic unit has 11 digit places, it is necessary that Tgmax- 1 2+" s) where n is the number of digit places of the sum producer. This does not mean that each sum appears in the sum producer 3 only a time interval T +nT after the occurrence of a control pulse, for each adder and carry producer becomes operative immediately upon receipt of information, that is to say the adders and carry producers V operate simultaneously if the digits of the numbers 1: and y are stored in the registers 1 and 2 simultaneously. The

output information of the adder 6 and of the carry:

producer 8 may still vary if at the instant T information about the carry c is received, the instant 0 being the instant at which the information about all the digits which are simultaneously stored in the registers 1 and 2 is available. The output information of the adder 6 and of the carry producer 8 may still vary if the information received about the carry 0 received from the preceding in the summation device a time interval nT after inyn.y1 'y2- l formation about digits x x x become available simultaneously. Hence, for high values of n the computing speed of the summation device is limited by the condition T ;T +nT This is a disad vantage as will be apparent from the fact that this time, interval is required infrequently only. Considered statistically, arbitrary additions of numbers written in the binary notation comprising forty digits require an average time interval of 4.6T for producing the sum of two numbers x and y in the summation device, so that a considerable decrease in computing rate is necessary for additions which occur only rarely.

FIG. 3 shows a possible embodiment of the members 4 5 6 7 8 The members 6 realize the Boolean expression:

14,1 t-1.014+ 1-1 1-244ht/14 1414 In the :above formulae the logical or function is symbolized as an addition (x+y signifies x or y), the logical and function is symbolized as a multiplication (xy signifies x and y), the logical negation is symbolized by a bar over a character (5 signifies not :4). The notation x indicates that the i digit of the number x is equal to 1 and 5; indicates that this digit is equal to 0. One. arrives at the Formula 2 by observing that 2 :1, if either only one of the three quantities x y 014,1 has the value 1, or all three quantities have the value 1. The Formula 3 expresses that c ;=l if at least two of the three quantities x y and c have the value 1 and the Formula 4 expresses that c .=O if at least two of the 0 three quantities have the value 0. p

The members 6 8 may be built up from and-gates A, or gates O and, desired, inverting gates I. FIG. 3

shows the structure of these members which is based directly upon the Expressions 2, 3, 4. Since each Boolean function may be expressed in its variables in an infinite number of equivalent manners, many further embodiments of the members 6 and 8 are possible. This remark applies of course to any logical member.

The member 7 may be built up in the manner described from two and-gates A and an inverting gate I. The inverting gate may be omitted if the member 6 produces not only the information z but also the information which formulas can be proved by induction. From the Formulas 2 and 8 it follows successively In these formulas, x and y, may be interchanged for any value of i occurring therein. The terms resulting from such interchanges are enclosed in brackets. On the basis of the Formulas 10 and analogous formulas which can be developed for E E E it is possible to design a sum producer without carry producers, in Which each digit Z1 is produced through two gates in series. This is the fastest sum producer that can be built with gates, but this solution requires a huge number of gates and hence of valves, crystal diodes or relays.

Another sum producer which is a little less 'fast though still extremely fast, is obtained by producing the informations z, and 2, via the informations c an'd E and producing the latter informations again via the informations i= iyn 1= i+yn 1= l+5h 1?! For this purpose the Formulas 2, 5, 8 and 9 are written On the basis of these formulas a summation device can be built which supplies all digits of the sum via at most three gates in series and consequently operates extremely fast; however the construction of this device also requires a huge number of gates and hence of tubes, crystm diodes, relays and so on. Assuming, for example, that each gate can supply its output information 20m seconds (=2().1O- seconds) after receipt of its input in formation, a summation device designed in accordance with these formulas can calculate, for any number of digit places, the sum of two binary numbers in 3.2012 seconds =60n seconds.

As has been mentioned hereinbefore, this extremely high computing speed frequently cannot be completely utilised for reasons extraneous to the summation device. The summation device may then be subdivided advantageously into sections each corresponding to more than one digit place and each section may be designed in the manner shown in FIG. 2, while allowance must be made for the fact that a carry must in certain cases traverse all digit places of a section. Three courses can be adopted, namely:

A. Each section is provided with an input carry pro- 6 ducer in which the carry traverses a small number of stages (three or two) and receives direct or indirect information about all digits x, and y, preceding this section. These inputs carry producers can produce the informations c, and 51411 by means of logical circuits based on the Formuias 14 and 15. All sections may then correspond to an equal number of digit places, with the exception of the first which, if no end-around-carry is produced, may comprise a few digit places more due to the absence of an input carry producer. In this event, the input carry producers openate simultaneously. The high carry producers (that is to say, carry producers 8 for high values of i), however, become very complicated in this solution and hence the following method B is preferred.

B. Each section is provided with an input carry producer in which the carry traverses two or three stages and receives as input information direct or indirect information about the digits x, and y, of the section preceding this section and the output information of the preceding input carry producer. In this case, each section must have a few digit places less than the preceding section, since the input carry producers now operate in series and a carry may traverse all input carry producers.

C. The methods A 'and B can be combined.

FIGS. 4a and 4b show diagrammatically the structure on the third and fourth sections of a summation device of the type B, the sections of which, taken from the first or extreme right to the last or extreme left, correspond successively to 8, =6, 5, 4, 3, 2, 1, digit places. Thus,- the third and fourth sections correspond to 5 and 4 digit places respectively. The adders 6 -6 and the carry prodimers 0,1 6,'h ac- 12,13 14,15' 1'ms 19,2o 21,22 8 824,25 and 826,27 may all have the form shown in FIG. 3. Thus, each adder 6 receives x 5,, y, and 5, as input information. In the figure, however, x and 5,, on the one hand, and y, and 5,, on the other hand, are represented by a single line and arrow. If, for that matter,

5 and ij, are not available as direct informations, this information may be produced from the informations x and y, by means of inverting gates. The adders 6, produce the information's z and 5, (the latter via an inverting gate, if required) and this is again indicated in the figure by a single line-land arrow each time. The address 6 also produce the indirect inform'ations d =x y' e =x +y fi =5 61:5 5 In 401 and 4b '[11686 four items of indirect information are each represented by a single line and The section 3 also comprises an input carry producer 116 which as input information receives the informations d,, e,, E '5 for i=8, 9, 10, 11', 12, 13 and the informations C2=C7,8, 5 :5 produced by the preceding input carry producer 10 From this information the input carry producer 1% produces the informations c =c and 5 :6 about the input carry of the third section. Similarly, the fourth section 3 of the summation device comprises an input carry producer 1%,. which receives the informations d e,, '01,, E, for i=l4, 15, 16, 17, 18 and also the informations c =c and E =E produced by the input carry producer 1%, and from these informations, produces the from which can be deduced:

D2 l3 1.30112 13 12d11 is iz n zo s s 4 18 181117 rs n m is rr m ia is n is is n 5 22 22 21 22 21 120 22 21 20 1s De zs 25 24 25 24 123 But, on the other hand However, this means that the input carries c c c c c 0; can be produced sequentially according to the Formulas 21 or 24 but that the end carry 0-; can also be produced simultaneously according to the Formula 25 from the information D E, (i=1, 2 7) which may also be used for the sequential production of the carriers c c c c c c Thus, the end carry 0-; can be simultane ously produced in a very fast manner without the use of an uncommonly large number of additional gates.

FIG. 6 shows the block-schematic diagram of a summation device based on the Formulas 24?, 25, which is subdivided into sections 3 3 3 3 3 3 3; corresponding to 8, 6, 5, 4, 3, 2, 1 digit places, respectively. The input carry producer of the second section receives the input information e d e d e d e d 2 01 e d a d 6 d-;, from which it produces the information D2=C2=C7'8; the input carry producer 10 of the third section receives the input informations 0 :0 e d e o, 10, lfia 11, u 12, 12 13 ie from which is P duces the informations E D and c =c the input carry producer 1% of the fourth section receives the informations 0 :0 14, 6 03 e die, 6m, iv, 1a, 18 7 from which it forms the information E D and C4=C13 1g; the input carry producer 10 of the fifth section receives the infofmations 4 1am, 19, 19 20, 211 21 21, 20, d e (1' e d from which it forms the informations E D and c =c the input carry producer 10 of the sixth section receives the informations c =c e d e (224, e d25 from fol'mS E6, D5 and C3=C2523; the input carry producer 10 of the seventh section receives the informations c =c e 6, dzs, e d from which it forms the informations E D and the end carry Cq=C27 23. The end carry producer '11 receives the informations 2 a 3 4 4 5 5 s e, 7 7 P duced in the input carry producers 10 to 10- from which it forms the end carry c =c according to Formula 25.

FIG. 7 shows the diagram of the input carry producer 1% based on the Formulas 22, 23 and 24.

FIG. 8 shows the diagram of an end carry producer 11 based on the formula 25.

Since the end carry c2128 is produced in two different manners, that is to say sequentially by the input carry producers 10 to 10 and simultaneously by the end carry producer 11, the end carries produced in these two manners can be compared with one another, the computer being stopped and an alarm signal being given when the two end carries so formed are unequal.

In some cases it may be of advantage to assume that the digits of the number produced by the adder are arranged on an imaginary circle (so that the last digit place is followed by the first), the carry being produced simultaneously at one or more places.

While the invention has been described with respect to a specific embodiment, it is to be understood that this is done for illustrative purposes only, the scope of the invention being delimited in the appended claims.

What is claimed is:

1. An arithmetic element for performing in the binary system the addition of two numbers x and y having a plurality of orders comprising: means for applying input electrical pulses to the element, said pulses representing the binary digits x, and y of the two numbers x and y, e

where x and y, are the binary digits at the 1" order of x and y, said arithmetic element being subdivided into sections, each section corresponding to a plurality of successive orders of the numbers x and y, the number of orders in any section being one less than the number of orders in the immediately preceding section, the k rsection comprising a first plurality of andand or-gates,

where k designates any arbitrary section, said gates being responsive to said input electrical pulses to produce first auxiliary pulses representing first auxiliary information d =x y and e =x +y each said section further comprising a second plurality of andand or-gates, said second plurality being responsive to said first auxiliary pulses to produce carry pulses representing carries of an addition operation and satisfying c =d +e c each k section except the first being preceded by an input-carry producer, means for applying to said input-carry producer the first auxiliary pulses from the (It-1W section representing the first auxiliary information d d d e e e where q is the order of the first and p is the order of the last digit position of the (k--l) section and means for applying to said input-carry producer carry pulses from the carry producer of the (k-l) section representing the input carry c =c of the (k-l) section, the input carry producer of the k section comprising a plurality of and-gates to the inputs of which are applied the pulses representing the first auxiliary information d d d e e the outputs of said carry-producer gates delivering pulses representing second auxiliary information e d e e d e e e d the input carry producer of the k section also comprising a first or-gate connected to receive the pulses representing said second auxiliary information and delivering pulses representing the information a first further and-gate having its input connected to the outputs of the gates delivering the information e 2 2 said and-gate delivering output pulses representing the information E =e e e e a second further and-gate having its input connected to said first further and-gate and to the output terminal of the input carry producer of the (k-1) section delivering pulses representing the information c =c the output of said second further and-gate delivering pulses representing the information E c a second or-gate the input of which is connected to the output of said second further and-gate and said first or-gate, said second or-gate 'delivering pulses representing the input carry .E D2, D

representing the information E D E E D E E E D where s is the number of sections, said end-carry producer further comprising an or-gate having its inputs connected to the outputs of said and-gates and to the output of the gate of the last input carry producer delivering the information D said last-mentioned or-gate producing pulses representing the end-carry 2. A high-speed adder for adding pulses corresponding to the operands of plural-order binary-numbers, comprising means for registering the pulses representing the respective order operand digits of said numbers, means for applying said pulses to said adder, said adder being divided into a plurality of sections, each section having a plurality of adding elements corresponding to a plurality of successive orders of said operands, the number of orders in any section being one less than the number of orders in the immediately preceding section, each sec tion except the one corresponding to the lowest order of said binary numbers being preceded by an input-carry producer, means in each section operating in response to a control pulse to produce sequentially the sum of the pulses applied to said section, the output of the inputcarry producer of each section being coupled to the input of the lowest order adding element of said section and also to the input of the input-carry producer of the immediately succeeding section, the inputs of the input-carry producer of each section being coupled to the outputs of the individual adding elements of the immediately preceding section and the output of the input-carry producer thereof, means in each input-carry producer operating in response to said control pulse to produce simultaneously an output independent of the sequential carries of the individual adding elements in the immediately preceding section and dependent on the sequential outputs of all the preceding input-carry producers, an end-carry producer having inputs connected to the outputs of all of said inputcarry producers, and means in said end-carry producer operating in response to said control pulse to produce simultaneously, independent of the intermediate carries,

the carry for the highest-order digit of the sum of said plural-order binary-numbers.

References Cited in the file of this patent UNITED STATES PATENTS 

1. AN ARITHMETIC ELEMENT FOR PERFORMING IN THE BINARY SYSTEM THE ADDITION OF TWO NUMBERS X AND Y HAVING A PLURALITY OF ORDERS COMPRISING: MEANS FOR APPLYING INPUT ELECTRICAL PULSES TO THE ELEMENT, SAID PULSES REPRESENTING THE BINARY DIGITS XI AND YI OF THE TWO NUMBERS X AND Y, WHERE XI AND YI ARE THE BINARY DIGITS AT THE ITH ORDER OF X AND Y, SAID ARITHMETIC ELEMENT BEING SUBDIVIDED INTO SECTIONS, EACH SECTION CORRESPONDING TO A PLURALITY OF SUCCESSIVE ORDERS OF THE NUMBERS X AND Y, THE NUMBER OF ORDERS IN ANY SECTION BEING ONE LESS THAN THE NUMBER OF ORDERS IN THE IMMEDIATELY PRECEDING SECTION, THE KTH SECTION COMPRISING A FIRST PLURALITY OF AND- AND OR-GATES, WHERE K DESIGNATES ANY ARBITRARY SECTION, SAID GATES BEING RESPONSIVE TO SAID INPUT ELECTRICAL PULSES TO PRODUCE FIRST AUXILIARY PULSES REPRESENTING FIRST AUXILIARY INFORMATION DI=XIYI AND EI=XI+YI, EACH SAID SECTION FURTHER COMPRISING A SECOND PLURALITY OF AND- AND OR-GATES, SAID SECOND PLURALITY BEING RESPONSIVE TO SAID FIRST AUXIALLY PULSES TO PRODUCE CARRY PULSES REPRESENTING CARRIES OF AN ADDITION OPERATION AND SATISFYING CI,I+1=DI+EICI-I,I, EACH KTH SECTION EXCEPT THE FIRST BEING PRECEDED BY AN INPUT-CARRY PRODUCER, MEANS FOR APPLYING TO SAID INPUT-CARRY PRODUCER THE FIRST AUXILIARY PULSES FROM THE (K-1)TH SECTION REPRESENTING THE FIRST AUXILIARY INFORMATION DQ,DQ+1 ... DP,EQ,EQ+1 ... EP, WHERE Q IS THE ORDER OF THE FIRST AND P IS THE ORDER OF THE LAST DIGIT POSITION OF THE (K-1)TH SECTION AND MEANS FOR APPLYING TO SAID INPUT-CARRY PRODUCER CARRY PULSES FROM THE CARRY PRODUCER OF THE (K-1)TH SECTION REPRESENTING THE INPUT CARRY CK-1=CQ-1,Q OF THE (K-1)TH SECTION, THE INPUT CARRY PRODUCER OF THE KTH SECTION COMPRISING A PLURALITY OF AND-GATES TO THE INPUTS OF WHICH ARE APPLIED THE PULSES REPRESENTING THE FIRST AUXILIARY INFORMATION DQ, DQ+1. . . DP, EQ, EQ+1. . . EP, THE OUTPUTS OF SAID CARRY-PRODUCER GATES DELIVERING PULSES REPRESENTING SECOND AUXIALLY INFORMATION EPDP-1 EPEP-1DP-2. . ., EPEP-1. . . EP+1DQ, THE INPUT CARRY PRODUCER OF THE KTH SECTION ALSO COMPRISING A FIRST OR-GATE CONNECTED TO RECEIVE THE PULSES REPRESENTING SAID SECOND AUXILIARY INFORMATION AND DELIVERING PULSES REPRESENTING THE INFORMATION 